1. Field of the Invention
The present invention relates to semiconductor devices, and, more particularly, to Field-Effect Transistors (FETs) and methods of fabricating the same.
2. Description of the Related Art
As semiconductor devices become highly integrated, problems associated with degradation of transistor characteristics may arise. Examples of these problems may include short channel effects such as punch-through, Drain Induced Barrier Lowering (DIBL), and subthreshold swing, as well as increased parasitic capacitance between the junction region and the substrate (i.e. a junction capacitor) and increased leakage current.
Double-gate field-effect transistors may overcome many of these problems. In a double-gate field-effect transistor, gate electrodes may be formed on both sides of the channel region of the transistor, and as such, may control both sides of the channel. As a result, short channel effects can be suppressed.
A Fin FET is a type of double-gate field-effect transistor. In a Fin FET, a silicon-on-insulator (SOI) substrate or a bulk substrate may be used. For example, a method for fabricating a Fin FET using a SOI substrate is disclosed in U.S. Pat. No. 6,413,802. FIG. 1 to FIG. 5 are cross-sectional views illustrating a method for fabricating a Fin FET according to U.S. Pat. No. 6,413,802.
FIG. 1 and FIG. 2 illustrate a semiconductor substrate 10, a buried oxide layer 12, and a SOI layer 14. Referring to FIG. 1, a hard mask 16 is formed on the SOI layer 14 to protect an upper portion thereof. Next, referring to FIG. 2, an etching mask pattern 18 for defining a silicon fin is formed on the hard mask 16.
Referring to FIG. 3, portions of the hard mask 16 and SOI layer 14 exposed by the etching mask pattern 18 are etched to form a silicon fin 14a. Referring to FIG. 4, after depositing a gate electrode material on the substrate 10, an etching mask 22 is formed on the gate electrode material. The gate electrode material left exposed by the etching mask 22 is then etched to form a transistor gate 20. Referring to FIG. 5, insulation layer spacers 24 are formed on both sidewalls of the gate 20.
A method for fabricating a Fin FET using a bulk substrate is disclosed in U.S. Pat. No. 5,844,278 and published U.S. Patent Application Publication No.2002/0011612. According to these methods, the bulk silicon substrate is etched to form a silicon fin. An insulation material is then formed to electrically isolate the silicon fin. Next, gate electrode material is deposited on the substrate over the fin. The gate electrode material is then etched to form a gate.
As compared to that of a conventional planar transistor (where a gate electrode is formed on a planar surface), the fabrication process for a Fin FET using a SOI substrate or a bulk substrate may form an “electrical bridge” between neighboring gate electrodes when the gates are formed on the substrate and the silicon fin projecting therefrom. In other words, neighboring gates may be electrically connected.
Accordingly, over-etching may be performed to prevent such an electrical bridge from being formed between neighboring gate electrodes. However, the sidewalls of silicon fins (i.e. the channel region) may be damaged by the etching process. For example, the thickness of the gate oxide layer may become thin at the edge of the gate due to over-etching, such that gate induced diode leakage (GIDL) may occur. Junction leakage current may be increased as well.